Frontend (ONNX/Relay/自定义DSL)
        │
        ▼
┌─────────────────────────────────────┐
│  MLIR Dialect Stack                 │
│  ┌───────────────────────────────┐  │
│  │ VideoDialect (高层语义)        │  │  ← 算子融合、图重写、布局推演
│  │   └─ video.resize, video.csc  │  │
│  ├───────────────────────────────┤  │
│  │ NPUDialect (硬件抽象)          │  │  ← 指令选择、寄存器分配、DMA调度
│  │   └─ npu.conv, npu.dma_copy   │  │
│  ├───────────────────────────────┤  │
│  │ VectorDialect / LLVM Dialect  │  │  ← 向量化、指令调度、寄存器压力控制
│  └───────────────────────────────┘  │
└─────────────────────────────────────┘
        │
        ▼
CodeGen → 动态库 / 内核元数据 → 运行时加载执行

// 示例：Resize算子定义
def Video_ResizeOp : Video_Op<"resize">,
    Arguments<(ins Variadic<AnyTensor>:$input,
                  DenseI64ArrayAttr:$output_shape,
                  StringAttr:$interp_mode,  // "bilinear" | "nearest" | "bicubic"
                  BoolAttr:$align_corners,
                  BoolAttr:$antialias)>,
    Results<(outs Variadic<AnyTensor>)>,
    Attrs<[Pure, SameOperandsAndResultElementType]> {
  let summary = "空间缩放算子，支持双线性/双三次/最近邻插值";
}

// 融合 Resize + ColorConvert + Normalize
struct FusePreprocessChain : public RewritePattern {
  FusePreprocessChain(MLIRContext* ctx) : RewritePattern(Video_ResizeOp::getOperationName(), 1, ctx) {}

  LogicalResult matchAndRewrite(Operation* op, PatternRewriter& rewriter) const override {
    auto resize = dyn_cast<Video_ResizeOp>(op);
    // 向后匹配 CSC -> Normalize -> Permute
    auto csc = getNextOp<Video_ColorConvertOp>(resize);
    auto norm = getNextOp<Video_NormalizeOp>(csc);
    auto perm = getNextOp<Video_PermuteOp>(norm);
    if (!csc || !norm || !perm) return failure();

    // 代价模型：估算融合后寄存器压力、TCM占用
    if (estimateRegisterPressure(resize, csc, norm, perm) > MAX_REG_PER_THREAD) 
      return failure();
    if (estimateTCMFootprint(resize, csc, norm, perm) > TCM_SIZE) 
      return failure();

    // 生成融合算子
    auto fused = rewriter.create<Video_FusedPreprocessOp>(op->getLoc(),
        resize.getInput(), resize.getOutputShape(),
        csc.getColorSpaceAttr(), norm.getMeanStdAttr(),
        perm.getPermutationAttr());
    rewriter.replaceOp(op, fused->getResults());
    // 删除中间算子
    rewriter.eraseOp(csc); rewriter.eraseOp(norm); rewriter.eraseOp(perm);
    return success();
  }
};

void buildVideoFusionPipeline(OpPassManager& pm) {
  // 1. 规范化：统一属性表示、展开广播
  pm.addPass(createVideoCanonicalizePass());
  
  // 2. 布局推演（前向传播首选布局，后向传播约束）
  pm.addPass(createVideoLayoutInferencePass());
  
  // 3. 贪心融合：大颗粒度模式优先
  pm.addPass(createVideoGreedyFusionPass());
  
  // 4. 融合后清理：消除Identity、折叠常量
  pm.addPass(createVideoCleanupPass());
  
  // 5. 降维至NPUDialect
  pm.addPass(createLowerVideoToNPUPass());
}

// NPU专用分块布局：NCHW -> N C/16 H W 16 (适配Tensor Core 16x16x16 MMA)
#npu.blocked_nchw16 = affine_map<(n,c,h,w) -> (n, c floordiv 16, h, w, c mod 16)>

// DMA友好双缓冲布局：在H维度插入ping-pong buffer stride
#npu.dma_double_buffer = affine_map<(n,c,h,w) -> (n, c, h, w, buffer_id)>

输入：融合后计算图 G = (V, E)，硬件约束 H
输出：每个张量的最优布局 L(v) ∈ LayoutSpace

1. 初始化：对每个算子 v，根据其内核模板设定首选布局集 P(v)
2. 迭代直到收敛：
   a. 前向传播：沿拓扑序，L(v) = argmin_{l∈P(v)} Cost(l, L(pred(v)))
   b. 后向传播：逆拓扑序，L(v) = argmin_{l∈P(v)} Cost(l, L(succ(v)))
   c. 全局代价评估：TotalCost = Σ EdgeCost(L(u), L(v)) + Σ NodeCost(v, L(v))
3. 若TotalCost下降 < 阈值，终止；否则回到步骤2

float EdgeCost(Layout src, Layout dst) {
  if (src == dst) return 0;                    // 零拷贝
  if (isViewCast(src, dst)) return 0.01;       // 视图转换，仅修改元数据
  return estimateDMACycles(src, dst) * BW_WEIGHT; // 实拷贝，按DMA周期计价
}

float NodeCost(Op op, Layout l) {
  // 结合内核模板查表：不同布局下的周期估算
  return KernelPerfModel::lookup(op.getName(), l).cycles * COMPUTE_WEIGHT;
}

NPUDialect (npu.fused_preprocess)
    │
    ├── Tile & Fuse (仿射循环变换) → scf.for + affine.map
    │
    ├── Vectorize (向量化) → vector.transfer_read/write + vector.contract
    │       └─ 关键：插值权重预计算常量传播、YUV→RGB矩阵乘法向量化
    │
    ├── Bufferize (缓冲区分配) → memref.alloc + memref.dealloc
    │       └─ 关键：TCM双缓冲分配、DMA描述符链构建
    │
    ├── LowerToLLVM (指令选择) → LLVM IR (含NPU内建函数)
    │
    └── CodeGen (MC层) → ELF共享库 + 元数据(JSON)

// 伪代码：融合内核主循环结构
__global void fused_preprocess_kernel(Args* args) {
  // 1. 预取首块数据到TCM Buffer A
  dma_issue_async(args->src, tcm_buf_A, tile_bytes);
  dma_wait();

  for (int tile_idx = 0; tile_idx < num_tiles; ++tile_idx) {
    int next_buf = (tile_idx + 1) % 2;
    void* compute_buf = (tile_idx % 2) ? tcm_buf_B : tcm_buf_A;
    void* prefetch_buf = (next_buf % 2) ? tcm_buf_B : tcm_buf_A;

    // 2. 异步预取下一块 (计算与DMA并行)
    if (tile_idx + 1 < num_tiles) {
      dma_issue_async(args->src + (tile_idx+1)*tile_bytes, 
                      prefetch_buf, tile_bytes);
    }

    // 3. 计算当前块：Resize + CSC + Norm + Permute (全向量化)
    //    - 双线性插值：定点数权重查表 + VFMAC
    //    - YUV→RGB：3x3矩阵乘向量化 (VLD128 + VFMA)
    //    - 归一化：乘加融合 (VFMUL + VFADD)
    //    - 输出直写NCHW16布局，无额外排布
    compute_tile(compute_buf, args->dst + tile_idx*out_tile_bytes, args->params);

    // 4. 等待下一块预取完成
    if (tile_idx + 1 < num_tiles) dma_wait();
  }
}

// kernel_meta.json 示例
{
  "kernel_name": "fused_preprocess_yolov8_1080p",
  "entry_point": "fused_preprocess_kernel",
  "tcm_requirement_bytes": 262144,
  "dma_channels": 2,
  "input_tensors": [
    {"name": "input", "layout": "NHWC", "dtype": "uint8", "shape": [1, 1080, 1920, 3]}
  ],
  "output_tensors": [
    {"name": "output", "layout": "NCHW16", "dtype": "fp16", "shape": [1, 3, 640, 640]}
  ],
  "compile_options": {"target_npu": "NPUv3", "opt_level": "O3"}
}

// 量化感知融合算子定义：显式建模量化参数作为编译期常量
def Video_QFusedPreprocessOp : Video_Op<"qfused_preprocess">,
    Arguments<(ins Variadic<AnyTensor>:$input,
                  // 静态量化参数：编译期常量折叠进指令立即数
                  DenseFP32ArrayAttr:$input_scale, DenseI32ArrayAttr:$input_zp,
                  DenseFP32ArrayAttr:$output_scale, DenseI32ArrayAttr:$output_zp,
                  // 算子语义属性
                  DenseI64ArrayAttr:$output_shape,
                  StringAttr:$interp_mode,
                  ArrayAttr:$csc_matrix,      // 3x4 行主序 [R_coeff; G_coeff; B_coeff; bias]
                  DenseFP32ArrayAttr:$norm_mean, DenseFP32ArrayAttr:$norm_std)>,
    Results<(outs Variadic<AnyTensor>)>,
    Attrs<[Pure, QuantizableResult]> {
  // 约束：输出必须为 per-tensor 量化 INT8/FP16
  let resultConstraints = [(QuantizationConstraint::PerTensor, [i8, f16])];
}

// Pass中集成精度守门人
struct QAwareFusionGuard : public RewritePattern {
  LogicalResult matchAndRewrite(Operation* op, PatternRewriter& rewriter) const override {
    // ... 匹配融合模式 ...
    
    // 1. 提取融合子图量化参数
    auto qParams = extractQuantParams(fusedSubgraph);
    // 2. 预测精度损失 (离线训练的XGBoost/LightGBM模型，推理<1ms)
    float predAccDrop = accuracyPredictor.predict(qParams, fusedSubgraph.getTopologyHash());
    
    // 3. 动态阈值：任务敏感度可配 (检测头前处理阈值严格，后处理可放宽)
    float threshold = getTaskSensitivityThreshold(op->getAttr("task_type")); 
    
    if (predAccDrop > threshold) {
      // 标记为"禁融合"，回退至分离量化方案
      op->emitWarning("QAF Guard: Predicted acc drop ") << predAccDrop 
          << " > threshold " << threshold << ", fallback to separate quant.";
      return failure(); 
    }
    return success();
  }
};

// 符号化形状定义
%H = dim %input, 1 : (tensor<?x?x3xui8>) -> index
%W = dim %input, 2 : (tensor<?x?x3xui8>) -> index
%out_H = floordiv(%H, %scale) : index  // 编译期已知scale=2
%out_W = floordiv(%W, %scale) : index

// 生成参数化内核入口
func @fused_preprocess_dyn(%arg0: tensor<?x?x3xui8>, %scale: index) -> tensor<?x?x3xf16> {
  // 循环边界使用符号 %out_H, %out_W
  scf.for %h = 0 to %out_H step %tile_H { ... }
}

class DynamicKernelManager {
  // 1. 形状规范化：将动态Shape映射至离散Bucket (如按32对齐)
  ShapeKey normalizeShape(ArrayRef<int64_t> dynShape) {
    return {align(dynShape[0], 32), align(dynShape[1], 32), dynShape[2], dynShape[3]};
  }

  // 2. 三级查找与编译
  KernelHandle getOrCompile(OpSeqKey opSeq, ShapeKey shape) {
    // L2: 完全特化缓存
    if (auto* h = l2Cache_.lookup({opSeq, shape})) return *h;
    
    // L1: 参数化模板实例化
    if (auto tmpl = paramTemplateRepo_.find(opSeq)) {
      auto handle = tmpl->instantiate(shape, /*fastPath=*/true); // 复用预编译的IR Module, 仅重做CodeGen
      if (handle) { l2Cache_.insert({opSeq, shape}, handle); return handle; }
    }
    
    // L0: 回退通用内核 (动态边界检查版本)
    return fallbackKernelRepo_.get(opSeq);
  }

  // 3. 后台异步热点升级 (Profile-Guided)
  void backgroundOptimize(OpSeqKey opSeq, ShapeKey shape, int hitCount) {
    if (hitCount > HOT_THRESHOLD && !l2Cache_.contains({opSeq, shape})) {
      threadPool_.enqueue([=]{
        auto handle = paramTemplateRepo_.find(opSeq)->instantiate(shape, /*fastPath=*/false); // 开启AutoTune
        l2Cache_.insert({opSeq, shape}, handle);
      });
    }
  }
};

struct DynamicTensorAllocator {
  // TCM划分：固定预留区(融合内核双缓冲) + 动态共享区(中间张量)
  static constexpr size_t TCM_TOTAL = 1024 * 1024; // 1MB
  static constexpr size_t TCM_FUSED_RESERVED = 256 * 1024; // 256KB 给最高优先级融合内核
  
  void* allocateTCM(size_t bytes, int alignment, int priority) {
    if (priority == HIGH && bytes <= TCM_FUSED_RESERVED) {
      return fusedPool_.allocate(bytes, alignment); // 无锁Bump Pointer
    }
    return sharedPool_.allocate(bytes, alignment); // Buddy System, 支持合并释放
  }
  
  // 编译期元数据指导运行时分配
  void planAllocation(const KernelMeta& meta, const ShapeKey& shape) {
    // 根据符号化推导的峰值TCM需求，预检查是否超限
    size_t peakTCM = meta.estimatePeakTCM(shape); 
    if (peakTCM > TCM_FUSED_RESERVED) {
      // 触发图重写：拆分融合链、启用DMA溢出到DDR
      triggerGraphResplit(meta, shape); 
    }
  }
};

// 设备拓扑描述 (由运行时注入)
#topology = #dist.topology<devices = [
  #dist.device<id=0, type="NPUv3", tcm=1MB, ddr_chan=2, pcie_gen=4>,
  #dist.device<id=1, type="NPUv3", tcm=1MB, ddr_chan=2, pcie_gen=4>,
  #dist.device<id=2, type="NPUv3", tcm=1MB, ddr_chan=2, pcie_gen=4>
], links = [
  #dist.link<src=0, dst=1, bw=32GB/s, latency=2us>, // NVLink-like
  #dist.link<src=1, dst=2, bw=32GB/s, latency=2us>
]>

// 划分后的模块标注
module @video_pipeline {
  // 子图0: SuperRes (Compute Bound) -> Device 0
  func @super_res(%arg0: tensor<1x3x720x1280xf16> @device(0)) -> tensor<1x3x1440x2560xf16> @device(0) { ... }
  
  // 子图1: YOLO Preprocess (Memory Bound) -> Device 1
  func @yolo_pre(%arg0: tensor<1x3x1440x2560xf16> @device(0)) -> tensor<1x3x640x640xf16> @device(1) 
      @dist.communicate<type=DMA_P2P, src=0, dst=1> { ... }
  
  // 子图2: YOLO Backbone+Head -> Device 1
  func @yolo_main(%arg0: tensor<1x3x640x640xf16> @device(1)) -> tensor<1x8400x85xf16> @device(1) { ... }
  
  // 子图3: DeepSORT Postprocess (Control Flow Heavy) -> Device 2 (CPU卸载或轻量NPU)
  func @deepsort_post(%arg0: tensor<1x8400x85xf16> @device(1)) -> tensor<?x7xf32> @device(2)
      @dist.communicate<type=DMA_P2P, src=1, dst=2> { ... }
}

// UTG 节点定义
struct UTGNode {
  KernelHandle kernel;           // 设备侧内核句柄
  DeviceID device;               // 目标设备
  vector<Event> deps;            // 依赖事件 (Compute Done / DMA Done)
  vector<DMADesc> recvDMAs;      // 入边DMA描述符链
  vector<DMADesc> sendDMAs;      // 出边DMA描述符链
  TCMReservation tcmPlan;        // TCM预留计划
};

// 调度器核心循环 (每设备一线程)
void DeviceScheduler::run(DeviceID dev) {
  while (running_) {
    auto readyNodes = dag_.getReadyNodes(dev); // 入度为0且设备匹配
    for (auto* node : readyNodes) {
      // 1. 提交入边DMA (Recv) - 异步
      for (auto& dma : node->recvDMAs) dma.submitAsync();
      
      // 2. 等待DMA + 依赖事件 (可配置Spin/Block)
      waitFor(node->deps); 
      waitForDMAs(node->recvDMAs);
      
      // 3. 启动计算内核 (已绑定TCM地址)
      node->kernel.launch(node->tcmPlan.getBaseAddr());
      
      // 4. 记录计算完成事件，提交出边DMA (Send)
      Event computeDone = node->kernel.recordEvent();
      for (auto& dma : node->sendDMAs) dma.submitAsync(computeDone); // 依赖计算完成
      
      dag_.markDone(node, computeDone);
    }
    // 批量轮询/中断等待，降低CPU占用
    waitForNextBatch(); 
  }
}

struct SafetyHardeningPass : public PassWrapper<SafetyHardeningPass, OperationPass<ModuleOp>> {
  void runOnOperation() override {
    ModuleOp module = getOperation();
    auto targetAttr = module->getAttrOfType<StringAttr>("target_as_level"); // "ASIL-B" / "ASIL-D"
    bool isASILD = (targetAttr && targetAttr.getValue() == "ASIL-D");

    module.walk([&](func::FuncOp func) {
      // 1. 关键内核入口：参数合法性检查 (指针非空、形状范围、对齐)
      insertInputValidation(func, isASILD);
      
      // 2. 循环边界显式检查 (防止索引越界导致TCM越界访问)
      func.walk([&](scf::ForOp forOp) {
        insertLoopBoundCheck(forOp, isASILD);
      });
      
      // 3. 双模冗余计算 (DMR) - 仅ASIL-D核心路径
      if (isASILD && func->hasAttr("safety_critical")) {
        applyDMRTransformation(func); // 复制函数体，插入比对逻辑
      }
      
      // 4. DMA描述符构建时插入CRC/ECRC计算
      func.walk([&](NPU_DMASetupOp dmaOp) {
        insertDMACRC(dmaOp);
      });
      
      // 5. 控制流完整性 (CFI) - 间接跳转/函数指针调用点插桩
      insertCFIChecks(func);
      
      // 6. 栈帧保护 (Stack Canary) - 函数入口/出口
      insertStackCanary(func);
    });
  }
};

; 原始内核入口
define void @fused_preprocess_kernel(ptr %input, ptr %output, ptr %params) { ... }

; DMR转换后
define void @fused_preprocess_kernel_DMR(ptr %input, ptr %output, ptr %params, ptr %status) {
entry:
  ; 1. 分配双份栈帧/寄存器上下文 (编译器自动着色)
  %ctx1 = alloca %ContextT, align 16
  %ctx2 = alloca %ContextT, align 16
  
  ; 2. 并行/串行执行两份拷贝 (视硬件线程资源)
  ;    策略A: 双线程并行 (双核NPU) -> 低延迟
  ;    策略B: 单线程时分复用 (单核) -> 低面积
  call void @fused_preprocess_kernel_Copy1(ptr %input, ptr %output, ptr %params, ptr %ctx1)
  call void @fused_preprocess_kernel_Copy2(ptr %input, ptr %output, ptr %params, ptr %ctx2)
  
  ; 3. 结果比对 (逐元素或关键特征值哈希比对)
  %cmp = call i1 @compare_results(ptr %output, ptr %output_shadow, %len)
  
  ; 4. 错误处理
  br i1 %cmp, label %ok, label %fail
  
ok:
  store i8 0, ptr %status  ; SUCCESS
  ret void

fail:
  ; 触发安全机制: 记录故障日志、置安全状态标志、触发看门狗复位
  call void @safety_error_handler(i32 ERR_DMR_MISMATCH)
  store i8 1, ptr %status  ; FAIL
  ret void
}

PyTorch (TorchScript) 
    │ torch-mlir (官方)
    ▼
ONNX Runtime / TensorRT 
    │ ONNX-MLIR / TensorRT-MLIR (官方/社区)
    ▼
MNN / NCNN / TFLite 
    │ MNN-Converter / NCNN-Converter (社区/自研)
    ▼
┌─────────────────────────────────────────────┐
│      VideoFrontendDialect (统一规范层)       │
│  - 算子语义标准化 (Resize/CSC/Norm/NMS...)   │
│  - 属性规范化 (Layout/Quant/DeviceHint)     │
│  - 动态Shape符号化                          │
└─────────────────────────────────────────────┘
    │ Legalize / Canonicalize (通用Pass)
    ▼
VideoDialect (领域优化层) → 后续流程复用

// 示例：Resize 语义对齐表
struct ResizeSemantics {
  enum class AlignCornersDefault { True, False, FollowFramework };
  enum class CoordinateTransform { AlignCorners, HalfPixel, Asymmetric, PyTorchDefault };
  enum class CubicCoeff { CatmullRom(-0.75), Mitchell(-0.5), Keys(-0.5) }; // 不同框架默认系数不同
};

// 转换规则实现
LogicalResult ConvertONNXResizeToVideo(ONNX_ResizeOp onnxOp, PatternRewriter& rewriter) {
  // 1. 提取ONNX属性
  auto mode = onnxOp.getMode(); // "nearest", "linear", "cubic"
  auto coordMode = onnxOp.getCoordinateTransformationMode(); // 默认 "half_pixel"
  auto cubicCoeff = onnxOp.getCubicCoeffA(); // 仅cubic模式有效
  
  // 2. 映射至VideoDialect标准语义
  Video_InterpolationMode videoMode;
  Video_CoordTransformMode videoCoord;
  FloatAttr videoCubicCoeff;
  
  if (mode == "linear") {
    videoMode = Video_InterpolationMode::Bilinear;
    // ONNX half_pixel == VideoDialect AlignCorners=False + HalfPixelOffset
    videoCoord = (coordMode == "align_corners") ? Video_CoordTransformMode::AlignCorners 
                                                : Video_CoordTransformMode::HalfPixel;
  } else if (mode == "cubic") {
    videoMode = Video_InterpolationMode::Bicubic;
    videoCubicCoeff = rewriter.getF32FloatAttr(cubicCoeff.value_or(-0.75)); // 补全默认值
    videoCoord = Video_CoordTransformMode::AlignCorners; // Bicubic通常配合align_corners
  }
  // ... 生成 Video_ResizeOp
}

// 标准插件 ABI (C接口，跨语言/编译器版本稳定)
typedef struct {
  const char* name;           // "npu_video_preprocess"
  uint32_t api_version;       // 1
  // 能力查询
  bool (*supports)(const OpDesc* op); 
  // 实例化 (编译/获取内核句柄)
  KernelHandle (*create)(const OpDesc* op, const DeviceContext* ctx);
  // 执行
  int (*execute)(KernelHandle handle, const Tensor* inputs, Tensor* outputs, StreamHandle stream);
  // 销毁
  void (*destroy)(KernelHandle handle);
} VideoPluginVTable;

// 导出符号 (编译器自动生成)
extern "C" __attribute__((visibility("default"))) 
const VideoPluginVTable* get_video_plugin_vtable() {
  static VideoPluginVTable vtable = {
    .name = "npu_video_preprocess_v3",
    .api_version = 1,
    .supports = &plugin_supports,
    .create = &plugin_create,
    .execute = &plugin_execute,
    .destroy = &plugin_destroy
  };
  return &vtable;
}

=== Kernel: fused_preprocess_yolov8_1080p ===
Target: NPUv3 (Vector Core x4 @ 1.2GHz, Peak 1.2 TFLOPS FP16, BW 64 GB/s)
--------------------------------------------------
| Metric                  | Value      | Bound    |
|-------------------------|------------|----------|
| Achieved Compute (TFLOPS)| 0.85       | 1.20 (71%)|
| Achieved Bandwidth (GB/s)| 42.3       | 64.0 (66%)|
| Arithmetic Intensity    | 20.1 FLOP/B| -        |
| Roofline Bound          | **Compute**|          |
|-------------------------|------------|----------|
| TCM Hit Rate            | 98.5%      | >95%     |
| DMA Overlap Ratio       | 92%        | >90%     |
| Vector Utilization      | 88%        | >85%     |
| Register Pressure       | 48/64      | < 56     |
--------------------------------------------------
Bottleneck Analysis:
  [1] Resize Bilinear Weight Calc: Scalar fallback (12% cycles) -> Optimize: Precompute LUT to TCM
  [2] CSC Matrix Mul: Partial vectorization (VLD64) -> Optimize: Promote to VLD128 + VFMAC
  [3] Tail Handling: Branch divergence (8% cycles) -> Optimize: Loop peeling + masked vector

# 运行时采样命令
npu-prof record --kernel=fused_preprocess_yolov8_1080p --duration=10s --event=cycles,stall_mem,stall_reg,vector_active

# 编译器辅助分析工具
npu-prof analyze --kernel=fused_preprocess_yolov8_1080p --mlir-ir=kernel.mlir --source=preprocess.py

Hotspot @ VideoDialect: video.resize (preprocess.py:42)
  MLIR Loc: "preprocess.py":42:15
  Assembly Region: 0x4000 ~ 0x43A0 (Loop Nest: h_tile -> w_tile -> channel)
  PMU Data:
    Cycles: 1,245,000 (32% total)
    Stall_Mem: 45% (L1 Miss -> TCM Bank Conflict on Weight LUT)
    Vector_Active: 68% (Width 128b, Ideal 100%)
  Compiler Suggestion:
    > Apply 'tcm_bank_padding' pass to weight LUT (pad 16B per row)
    > Enable 'vector_width_256' target feature (requires NPUv3.1+)

# 自动调优搜索空间定义 (Python DSL)
@autotune_config
class FusedPreprocessTuneConfig:
    # 循环变换
    tile_h = knob([16, 32, 64, 128])      # H维度分块
    tile_w = knob([16, 32, 64, 128])      # W维度分块
    unroll_inner = knob([1, 2, 4, 8])     # 内层展开
    
    # 布局变换
    output_layout = choice([NCHW16, NHWC8, NCHW32])
    
    # 双缓冲策略
    double_buffer = bool_knob()
    dma_burst_len = knob([64, 128, 256, 512]) # Bytes
    
    # 约束
    constraints = [
        lambda cfg: cfg.tile_h * cfg.tile_w * 3 * 2 <= 256*1024, # TCM容量约束
        lambda cfg: cfg.tile_h % 16 == 0,                         # 对齐约束
    ]

# 调优流程 (离线/在线)
tuner = AutoTuner(target="NPUv3", trials=200, early_stop=20)
best_config = tuner.tune(kernel_ir, calib_data)
# 产出: 专用内核变体 + 更新 KernelMeta.json

timeline
    title 编译器基础设施演进路线
    2023 Q4 : 单NPU静态融合内核生成 (v1.0)
            : 支持固定Shape/精度前处理链
    2024 Q2 : 量化感知融合 + 动态Shape JIT (v2.0)
            : INT8/FP16混合精度、三级缓存JIT
    2024 Q4 : 多NPU协同划分 + 安全插桩 (v3.0)
            : 任务图划分、DMR自动生成、ASIL-D交付
    2025 H1 : 全栈自动调优 + 生态标准化插件 (v4.0)
            : Roofline指导、AutoTune闭环、TRT/ORT/MNN零成本接入
    2025 H2 : 大模型多模态前处理原生支持 (v5.0)
            : 动态分辨率ViT Patchify、文本/音频联合预处理融合
            : 编译器驱动的稀疏/低秩近似自动注入

graph TD
    A[Input: ONNX/TorchScript] --> B[Frontend Legalize to VideoFrontendDialect]
    B --> C[Canonicalize & Shape Inference]
    C --> D[Quantization Annotation Insertion]
    D --> E[VideoDialect Legalize]
    E --> F[Layout Inference & Propagation]
    F --> G[Quantization-Aware Fusion (QAF)]
    G --> H[Greedy Fusion + Cost Model]
    H --> I[Distributed Partitioning (Optional)]
    I --> J[NPUDialect Legalize]
    J --> K[Tile & Fuse (Affine Loop Opt)]
    K --> L[Vectorization + TCM Buffer Alloc]
    L --> M[Safety Hardening (DMR/CFI/CRC)]
    M --> N[DMA Double Buffer Insertion]
    N --> O[Lower to LLVM Dialect]
    O --> P[Instruction Selection & Scheduling]
    P --> Q[CodeGen: ELF + Meta JSON]
    Q --> R[Runtime: Plugin Load & UTG Schedule]

# compiler_config.yaml
target:
  npu_version: "NPUv3"
  tcm_size_kb: 1024
  vector_width: 128
  tensor_core_mma: [16, 16, 16] # M, N, K
  dma_channels: 4
  pcie_gen: 4

optimization:
  fusion:
    enable_qaf: true
    max_fused_ops: 8
    tcm_budget_ratio: 0.8
    accuracy_guard_threshold: 0.005 # mAP drop
  layout:
    solver: "joint_iterative"
    max_iterations: 10
    preferred_layouts: ["NCHW16", "NHWC8", "NCHW32"]
  jit:
    cache_levels: 3
    hot_threshold: 100
    autotune_trials: 200
  safety:
    asil_level: "ASIL-B" # or "ASIL-D"
    dmr_mode: "dual_core_parallel" # or "single_core_timeshare"
    cfi_level: "full" # "none", "basic", "full"

deployment:
  plugin_abi_version: 1
  runtime_log_level: "INFO"
  enable_profiling: true